1. Field of the Invention
The invention relates generally to a bootstrap circuit, and more particularly to, a word line bootstrap circuit for implementing a high-speed flash memory and a memory cell having a good data holding capability.
2. Description of the Prior Art
Generally, in order to increase the speed of a read operation in a flash memory cell driven with a low voltage upon a read operation, a low potential supply voltage (LOW Vcc; LVcc) is bootstrapped using a bootstrap circuit to supply the bootstrapped voltage to a word line.
In case that the bootstrap circuit is used to boost the word line voltage, there is a problem of a retention since it is difficult to exactly read the cell current if the word line voltage boosted by the bootstrap circuit is too low and stress is applied to the cell gate if the word line voltage is too high. Therefore, the word line voltage boosted by the bootstrap circuit must be boosted within a given range of voltage.
Referring now to FIG. 1, a construction of a conventional word line bootstrap circuit will be below explained.
The conventional word line bootstrap circuit includes a first stage 10xcx9cthird stage 30 for pumping the supply voltage xe2x80x98Vccxe2x80x99 applied to the word line over three steps.
The first stage 10 includes a first precharging unit 11 for precharging a first node Q1 with a given potential xe2x80x98Vccxe2x80x99 or xe2x80x98Vccxe2x88x92Vtxe2x80x99 depending on a first clock signal CLK1, and a first capacitor C1 for pumping the first node Q1 with a first potential xe2x80x98V1xe2x80x99 depending on a kick signal KICK.
The second stage 20 includes a second precharging unit 21 for precharging a second node Q2 with a given potential xe2x80x98Vccxe2x80x99 or xe2x80x98Vccxe2x88x92Vtxe2x80x99 depending on the first clock signal CLK1, a first PMOS transistor P1 connected between the first node Q1 and the third node Q3 and driven by a second clock signal CLK2, a first NMOS transistor N1 connected between the third node Q3 and the ground Vss and driven by a third clock signal CLK3, and a second capacitor C2 connected between the second node Q2 and the third node Q3, for pumping the second node Q2 with a second potential xe2x80x98V2xe2x80x99.
The third stage 30 includes a third precharging unit 31 for precharging a fourth node Q4 with a given potential xe2x80x98Vccxe2x80x99 or xe2x80x98Vccxe2x88x92Vtxe2x80x99 depending on the first clock signal CLK1, a second PMOS transistor P2 connected between the second node Q2 and the fifth node Q5 and driven by the second clock signal CLK2, a second NMOS transistor N2 connected between a fifth node Q5 and the ground Vss and driven by the third clock signal CLK3, and a third capacitor C3 connected between the fourth node Q4 and the fifth node Q5, for pumping the fourth node Q4 with the third potential xe2x80x98V3xe2x80x99.
A method of driving the conventional word line bootstrap circuit constructed as above will be below described by reference to FIG. 2 showing a waveform of each of signal inputted respective stages.
Referring now to FIG. 2, during period from a first time T0 to a second time T1, the first, the second and third clock signals CLK1, CLK2 and CLK3 are kept at a LOW state and the kick signal KICK are kept to be at HIGH state.
In this state, at the second time T1, if the first, second and third clock signals CLK1, CLK2 and CLK3 are shifted from a LOW state to a HIHG state and the kick signal KICK is shifted from a HIGH state to a LOW state, in a positive edge period where the state is changed to a HIGH state, the first, the second and third pre-charging units 11, 21 and 31 are driven by the first clock signal CLK1, the first and second PMOS transistors P1 and P2 are turned off by the second clock signal CLK2 and the first and second NMOS transistors N1 and N2 are turned on by the third clock signal CLK3.
Therefore, a current path is formed between the first precharging unit 11 and a source of the kick signal KICK to pre-charge the first pre-charging unit 11 with the supply voltage xe2x80x98Vccxe2x80x99 outputted from the first capacitor C1, so that the first node Q1 is precharged with the potential of the supply voltage xe2x80x98Vccxe2x80x99. Also, a current path is formed between the second precharging unit 21 and the ground Vss through the first NMOS transistor N1 to precharge the second capacitor C2 with the supply voltage xe2x80x98Vccxe2x80x99 outputted from the second precharging unit 21, so that the second node Q2 is precharged with the potential of the supply voltage xe2x80x98Vccxe2x80x99. Also, a current path is formed between the third precharging unit 31 and the ground Vss through the second NMOS transistor N2 to precharge the third capacitor C3 with the supply voltage xe2x80x98Vccxe2x80x99 outputted from the third precharging unit 31, so that the fourth node Q4 is precharged with the potential of the supply voltage xe2x80x98Vccxe2x80x99.
In a period from the second time T1 to a third time T2, the first, the second and the third clock signals CLK1, CLK2 and CLK3 are kept at a HIGH state the kick signal KICK is kept at a LOW state. Thus, the potential of the first node Q1, the second node Q2 and the fourth node Q4 maintain the potential of the supply voltage xe2x80x98Vccxe2x80x99.
In this state, at third time T2, if the first, the second and third clock signals CLK1, CLK2 and CLK3 are shifted from a HIGH state to a LOW state and the kick signal KICK is shifted from a LOW state to a HIGH state, in a negative edge period where the state is changed to a LOW state, the first, the second and the third pre-charging units 11, 21 and 31 are not driven by the first clock signal CLK1, the first and second PMOS transistors P1 and P2 are turned on by the second clock signal CLK2, and the first and second NMOS transistors N1 and N2 are turned off by the third clock signal CLK3.
Therefore, the first potential xe2x80x98V1xe2x80x99 on the first node Q1 is increased by a potential corresponding to the kick signal KICK. For example, if the potential of the kick signal KICK is xe2x80x98Vccxe2x80x99 same to the supply voltage xe2x80x98Vccxe2x80x99, the first potential xe2x80x98V1xe2x80x99 is increased by xe2x80x982Vccxe2x80x99. Then, the second potential xe2x80x98V2xe2x80x99 on the second node Q2 is increased by xe2x80x983Vccxe2x80x99 since the first potential xe2x80x98V1xe2x80x99 is transmitted through the first PMOS transistor P1 that was turned on by the second clock signal CLK2. Also, the third potential xe2x80x98V3xe2x80x99 on the fourth node Q4 is increased by xe2x80x984Vccxe2x80x99 since the second potential V2 is transmitted through the second PMOS transistor P2 that was turned on by the second clock signal CLK2. Therefore, a boosting voltage Vboot outputted to an output terminal of a final word line bootstrap circuit is increased by xe2x80x984Vccxe2x80x99.
As described above, the boosting voltage Vboot outputted to the output terminal of the conventional word line bootstrap circuit can be represented by a following Equation 1.
Vboot=xcex1V2+Vcc=xcex1(xcex1V1+Vcc)+Vcc=xcex1{xcex1(xcex1Vcc+Vcc)+Vcc}+Vcc=xcex1{xcex12Vcc+xcex1Vcc+Vcc}+Vcc=xcex13Vcc+xcex12Vcc+xcex1Vcc+Vcc=(xcex13+xcex12+xcex1+1)Vccxe2x80x83xe2x80x83[Equation 1]
where xe2x80x98xcex1xe2x80x99 is the coupling ratio of capacitors in respective stages.
If the coupling ratio xe2x80x98xcex1xe2x80x99 of capacitors constituting respective stages is xe2x80x9c1xe2x80x9d, the boosting voltage Vboot is 4Vcc according to Equation 1. At this time, what the coupling ratio xe2x80x98xcex1xe2x80x99 is xe2x80x9c1xe2x80x9d means that the capacitor transmits 100% boosting voltage Vboot. Generally, the coupling ratio xe2x80x98xcex1xe2x80x99 of a capacitor is about 0.6xcx9c0.7(60xcx9c70%).
In other words, as represented in Equation 1, a problem in the conventional word line bootstrap circuit is that if the coupling ratio xe2x80x98xcex1xe2x80x99 of the capacitor is determined, the boosting voltage Vboot is changed in proportion to Vcc. For example, in a Vcc operation of 1.6xcx9c2V, the sum of the coupling ratio xe2x80x98xcex1xe2x80x99 of a capacitor constituting all the stages is xe2x80x9c3xe2x80x9d (i.e., (xcex13+xcex12+xcex1+1)=3)), the voltage range of the boosting voltage Vboot is increased to 4.8xcx9c6V.
In other words, a target specification of a general word line voltage is swung in the range of 1V. However, the swing range in the boosting voltage Vboot of the conventional word line bootstrap circuit goes beyond the target specification of the word line voltage. Due to this, a margin of the word line voltage could not secured and a general target specification range could not be also secured. In addition, in a high potential supply voltage (HIGH Vcc; HVcc) flash memory cell, a conventional word line bootstrap circuit can be applied by forming the coupling ratio of a capacitor to be small. Even in this case, a margin of the word line voltage could not be secured and a read operation could not be stably performed.
The present invention is contrived to solve the above problems and an object of the present invention is to stably perform a read operation of a flash memory cell in which a bootstrap circuit is constructed to be clamped only at a high potential voltage xe2x80x98HVccxe2x80x99 and to be normally operated at a low potential voltage source xe2x80x98LVccxe2x80x99 to easily control on a word line boosting voltage, by sensing the high potential voltage source xe2x80x98HVccxe2x80x99 and the low potential voltage source xe2x80x98LVccxe2x80x99.
In order to accomplish the above object, a boosting voltage generator according to the present invention is characterized in that it comprises a supply voltage level detection unit for detecting a high potential supply voltage and a potential supply voltage using a reference voltage; and a boosting voltage generator for controlling the level of a boosting voltage depending on a clamp signal generated by an output signal of the supply voltage level detection unit.
Also, a boosting voltage generator according to the present invention is characterized in that it comprises a supply voltage level detection unit for detecting a high potential supply voltage and a potential supply voltage using a reference voltage; and a clamp signal generating unit for generating a clamp signal depending on an output signal of the supply voltage level detection unit; and a boosting voltage generator for controlling the level of a boosting voltage depending on the clamp signal.